Design And Reuse SoC News Alert

September 7, 2004

Welcome to issue of September 7, 2004 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

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OCP-IP 2.0 PSL Checker from HDL Design House

PCI Express Root and EP dual mode (dynamical switching), PCI Express Switch Port Core and PCI express Root Complex Port Core from Cascade Semiconductor

MPEG4 Encoder (CIF) from Global UniChip

Hi-Speed USB 2.0 On-The-Go PHY from Synopsys

HDTV Video Front End from ChipIdea Microelectronics

Wanted IPs :

USB 1.1 OTG Transceiver

Low leakage SRAM/Logic for UMC 0.18u std cmos process

Bluetooth headset solution

'Symmetric' design technique facilitates power analysis

Multi-Ports Eliminate Baseband Processing Bottlenecks

Interview - Rajeev Madhavan, chairman and CEO of Magma Design: Intellectual Propriety (by Ed Sperling, Electronic News)

ASIC design starts to halt decline, says iSuppli

IP/SOC PRODUCTS

TransEDA Announces PCI All-in-One Verification IP and VN-Control 3.0 for PCI Express, PCI-X and PCI Based Designs

TriCN partners with PLDApplications for full PCI Express solution

Genesys Logic Introduces PCI Express and GigaSata Serial ATA Products at Intel Develop Forum

RF Engines launches SpectraChip, a digital replacement for analogue intermediate frequency (IF) filtering used in current spectrum analysers

Faraday Technology Introduces Industry's Smallest PCI-Express Solution at UMC 0.13um

Tensilica Announces Major IC Design Automation Breakthrough, The Automatic Generation of Optimized Programmable RTL Engines from Standard C Code

Pioneering DSP core breaks more ground with new processing modules

Intellectutal Property Support For New FPGA Familes Announced By Lattice Semiconductor And CAST Incorporated

Dolphin's Read-Only Memory generator embeds the highest density on standard CMOS

STRUCTURED ASIC

LSI Logic Debuts Innovative SAS and SATA II Storage Adapters and Platform ASIC Methodology at Intel Developer Forum

LSI Logic Offers Complete PCI Express Solution For Rapidchip Platform ASIC

DEALS

AMI Semiconductor Chooses ARM To Drive Automotive Electronics For Information, Performance And Safety In Cars

Ambarella licenses the World's First Standard SD MMC 4.0 Host Controller IP core from Arasan Chip Systems

BUSINESS

Memec Insight Becomes New Distributor of Nordic Semiconductor ASA in Europe

ASICS World Services, LTD, Joins Xilinx AllianceCORE and Common License Consortium Programs

Coreworks and Prototyping-Japan agreement to promote and distribute digital audio and video IP coresCoreworks and Prototyping-Japan agreement to promote and distribute digital audio and video IP cores and evaluation boards in the Japanese market and

Monolithic System Technology, Inc. Announces Grant of Stock Options

Samsung Semiconductor Teams with Denali to Accelerate OneNAND Flash Adoption

FINANCIAL RESULTS

Altera pre-announces shortfall for Q3

LEGAL

Court Awards MOSAID Monetary Sanctions in Lawsuit Against Samsung

PEOPLE

Xilinx announces new DSP division, industry veteran Omid Tahernia named Vice President and General Manager

EMBEDDED SYSTEMS

EVE Unveils ZeBu-XL, the Electronics Industry's First High-End Prototyping Solution

SIDSA announces the new "CARMeN-II" ARM emulation board for SoC Development &Validation

Accelerated Technology's Nucleus EDGE Next Generation Development Environment Ushers In New Era of Eclipse Platform Use

Intel will demo its first multi-core CPU at IDF

Atmel Introduces a Complete Biometric System for Easy Integration Into Customer Applications

FOUNDRIES

SMIC looks to China's fabless firms, touts 90-nm

FPGA/CPLD

Xilinx executes on FPGA processor leadership strategy, forms new embedded processing division

Pirelli Chooses Altera Stratix GX Devices for Radio-Over-Fiber 3G Network Solution

Altera Introduces Stratix II Development Kits for High-Speed, DSP, and Embedded System Designs

Altera's New MAX II Development Kit Simplifies Low-Cost CPLD Design

SPONSORED BY: TEMENTO SYSTEMS

Temento Systems, innovative provider of test, debug and verify solutions for FPGA and Hardware Platforms now offer two Edition of its DiaLite On-Chip Instrumentation tool. The new HDL Fault Finder IP included into the Power Edge Edition allows accurate monitoring and display of logic events contained into your HDL code. Designers have now the possibility to insert Watchpoints and Breakpoints on the instruments and into the code, and make it run concurrently to the instrumentation.

Click here to know more about Temento

IP/SOC 2004
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December 8-9, 2004

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